Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
56
MCP MEMORY
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This Mobile SDR SDRAM is organized as four independent
banks of 4,194,304 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 2,097,152 words x 32 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16 1/CS
This Mobile SDR SDRAM is organized as four independent
banks of 8,388,608 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 16 2/CS
This Mobile SDR SDRAM is organized as two chips which have
four independent banks of 4,194,304 words x 16 bits memory
arrays. The BA0 ~ BA1 inputs are latched at the time of assertion
of RAS and CAS to select the bank to be used for the operation.
The bank addresses BA0 ~ BA1 are latched at bank active, read,
write, mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 4,194,304 words x 32 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16 1/CS
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA0 ~ BA1 dur-
ing read or write command.
: In case x 16 2/CS
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
ADDRESSES of 256Mb ADDRESSES of 512Mb
A. DEVICE OPERATIONS (continued)