Samsung SC32442B54, Руководство пользователя

Страница: 232 / 647

SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT
7
-
23
PLL CONTROL REGISTER (MPLLCON & UPLLCON)
Register Address R/W Description Reset Value
MPLLCON 0x4C000004 R/W MPLL configuration register 0x00096030
UPLLCON 0x4C000008 R/W UPLL configuration register 0x0004d030
PLLCON Bit Description Initial State
MDIV [19:12] Main divider control 0x96 / 0x4d
PDIV [9:4] Pre-divider control 0x03 / 0x03
SDIV [1:0] Post divider control 0x0 / 0x0
NOTE
When you set MPLL&UPLL values, you have to set the UPLL value first and then the MPLL value. (Needs intervals
approximately 7 NOP)
PLL VALUE SELECTION TABLE
It is not easy to find a proper PLL value. So, we recommend referring to the following PLL value recommendation
table.
Input Frequency Output Frequency MDIV PDIV SDIV
12.0000MHz 48.00 MHz
(Note)
80 8 1
12.0000MHz 96.00 MHz
(Note)
80 8 0
12.0000MHz
300.00 MHz 67 1 1
16.9344MHz 47.98 MHz
(Note)
26 4 1
16.9344MHz 95.96 MHz
(Note)
26 4 0
16.9344MHz
296.352
MHZ
62 2 1
16.9344MHz 400 MHz 63 4 0
16.9344MHz 500 MHz 110 2 1
NOTE
The 48.00MHz and 96MHz output is used for UPLLCON register.