Samsung SC32442B54, Руководство пользователя

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SC32442B RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT
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CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER
Register Address R/W Description Reset Value
CAMDIVN 0x4C000018 R/W Camera clock divider register 0x00000000
CAMDIVN Bit Description Initial State
DeepSTOP_EN [16] 0:DeepSTOP_EN is Off.
1:DeepSTOP_EN is ON
This bit is valid when CLKCON[0]=1.
DVS_EN [12] 0:DVS OFF
ARM core will run normally with FCLK (MPLLout).
1:DVS ON
ARM core will run at the same clock as system clock (HCLK).
0
Reserved [11] 0
Reserved [10] 0
HCLK4_HALF [9] HDIVN division rate change bit, when CLKDIVN [2:1]=10b.
0: HCLK = FCLK/4
1: HCLK= FCLK/8
Note1)
Refer the CLKDIV register.
0
HCLK3_HALF [8]
HDIVN division rate change bit, when CLKDIVN [2:1]=11b.
0: HCLK = FCLK/3
1: HCLK= FCLK/6
Note1)
Refer the CLKDIV register.
0
CAM3CK_SEL [5] 0:Enable divide factor setting register; CMACLK_DIV [3:0].
1:UPLL output / 3
UPLL/3 is valid when CAMCLK_SEL=1 0
CAMCLK_SEL [4] 0:Use CAMCLK with UPLL output (CAMCLK=UPLL output).
1:CAMCLK_DIV value or 3 divide CAMCLK. 0
CAMCLK_DIV [3:0] CAMCLK divide factor setting register (0 – 15).
Camera clock = UPLL / [(CAMC1) x2].
This bit is valid when CAMCLK_SEL=1 & CAM3CK_SEL=0.
0
Note1) In case of power on reset, If you want to use FCLK/8 or FCLK/6, CAMDIVN(HCLK4_HALF/HCLK3_HALF)
register is setting after MPLLCON set