Samsung SC32442B54, Руководство пользователя

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I/O PORTS S3C2442B RISC MICROPROCESSOR
9-8
I/O PORT CONTROL REGISTER
PORT A CONTROL REGISTERS(GPACON, GPADAT)
Register Address R/W Description Reset Value
GPACON 0x56000000 R/W Configures the pins of port A 0xffffff
GPADAT 0x56000004 R/W The data register for port A Undef.
Reserved 0x56000008 - Reserved Undef
Reserved 0x5600000c - Reserved Undef
GPACON Bit Description
GPA24 [24] reserved
GPA23 [23] reserved
GPA22 [22] 0 = Output 1 = nFCE
GPA21 [21] 0 = Output 1 = nRSTOUT
GPA20 [20] 0 = Output 1 = nFRE
GPA19 [19] 0 = Output 1 = nFWE
GPA18 [18] 0 = Output 1 = ALE
GPA17 [17] 0 = Output 1 = CLE
GPA16 [16] 0 = Output 1 = nGCS[5]
GPA15 [15] 0 = Output 1 = nGCS[4]
GPA14 [14] 0 = Output 1 = nGCS[3]
GPA13 [13] 0 = Output 1 = nGCS[2]
GPA12 [12] 0 = Output 1 = nGCS[1]
GPA11 [11] 0 = Output 1 = ADDR26
GPA10 [10] 0 = Output 1 = ADDR25
GPA9 [9] 0 = Output 1 = ADDR24
GPA8 [8] 0 = Output 1 = ADDR23
GPA7 [7] 0 = Output 1 = ADDR22
GPA6 [6] 0 = Output 1 = ADDR21
GPA5 [5] 0 = Output 1 = ADDR20
GPA4 [4] 0 = Output 1 = ADDR19
GPA3 [3] 0 = Output 1 = ADDR18
GPA2 [2] 0 = Output 1 = ADDR17
GPA1 [1] 0 = Output 1 = ADDR16
GPA0 [0] 0 = Output 1 = ADDR0
(Note) The GPA21 Power is depend on VDDOP, the other pads(GPA0~20, GPA22~24) are all on VDDMOP.