Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
11
MCP MEMORY
CAPACITANCE
(
T
A
=25
°
C, V
CC
=3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Condition Min Max Unit
Input/Output Capacitance C
I/O
V
IL
=0V - 10 pF
Input Capacitance C
IN
V
IN
=0V - 10 pF
VALID BLOCK
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
Parameter Symbol Min Typ. Max Unit
2Gb N
VB
2,008 - 2,048 Blocks
AC TEST CONDITION
(TA=-25 to 85
°
C,Vcc=1.7~1.95V unless otherwise noted)
Parameter Value
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc/2
Output Load 1 TTL GATE and CL=30pF
MODE SELECTION
NOTE : 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE ALE CE WE RE WP Mode
H L L H X
Read Mode
Command Input
L H L H X Address Input(5clock)
H L L H H
Write Mode
Command Input
L H L H H Address Input(5clock)
L L L H H Data Input
L L L H X Data Output
X X X X H X During Read(Busy)
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
X X (1) X X X L Write Protect
X X H X X 0V/V
CC
(2) Stand-by