Samsung SC32442B54, Руководство пользователя

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SC32442B RISC MICROPROCESSOR ELECTRICAL DATA
25-
37
Table 25-6 ROM/SRAM Bus Timing Constants
(V
DDiarm
= 1.7V
±
0.05 V, V
DDi
= 1.2V
±
0.05 V, T
A
= -25 to 85
°
C, V
DDMOP
= 1.8V
±
0.1V)
Parameter Symbol
Min
(V
DDMOP
= 1.8V)
Typ
Max
(V
DDMOP
= 1.8V)
Unit
ROM/SRAM Address Delay
t
RAD
3 – 7 ns
ROM/SRAM Chip Select Delay
t
RCD
3 – 7 ns
ROM/SRAM Output Enable Delay
t
ROD
3 – 6 ns
ROM/SRAM Read Data Setup Time.
t
RDS
2 – - ns
ROM/SRAM Read Data Hold Time.
t
RDH
0 – - ns
ROM/SRAM Byte Enable Delay
t
RBED
3 – 7 ns
ROM/SRAM Write Byte Enable Delay
t
RWBED
3 – 7 ns
ROM/SRAM Output Data Delay
t
RDD
2 – 7 ns
ROM/SRAM External Wait Setup Time
t
WS
4 – - ns
ROM/SRAM External Wait Hold Time
t
WH
0 – - ns
ROM/SRAM Write Enable Delay
t
RWD
3 – 7 ns
Table 25-7 Memory Interface Timing Constants
(V
DDiarm
= 1.4V
±
0.05 V, V
DDi
= 1.2V
±
0.05 V, T
A
= -25 to 85
°
C, V
DDMOP
= 1.8V
±
0.1V, 100MHz, CL=50pF)
Parameter Symbol Min Typ Max Unit
SDRAM Address Delay
T
SAD
1.60 – 5.17 ns
SDRAM Chip Select Delay
T
SCSD
1.29 – 4.42 ns
SDRAM Row Active Delay
T
SRD
1.41 – 5.14 ns
SDRAM Column Active Delay
T
SCD
1.41 – 5.28 ns
SDRAM Byte Enable Delay
T
SBED
1.31 – 5.64 ns
SDRAM Write Enable Delay
T
SWD
1.41 – 5.28 ns
SDRAM Read Data Setup Time
T
SDS
2 – – ns
SDRAM Read Data Hold Time
T
SDH
1.5 – – ns
SDRAM Output Data Delay
T
SDD
1.37 – 5.62 ns
SDRAM Clock Enable Delay
T
cked
1.59 – 3.81 ns