Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
64
MCP MEMORY
t
RDL =2CLK
t
DAL
4)
=
t
RDL +
t
RP
Note:
1) To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2) DQM should be issued to inhibit invalid write.
3) This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank pre-
charge of four banks operation.
t
RDL
1)
A
B
Note:
1) SAMSUNG support tRDL=2CLK(or 15ns) for
Mobile SDR SDRAM
.
2) Number of valid output data after row precharge : A, B for CAS Latency = 2, 3 respectively.
3) The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal
4) tDAL defined Last data in to Active delay. SAMSUNG can support tDAL=tRDL+ tRP .
Auto Precharge Starts
3)
2)
3)
2)
5. Write Interrupted by Precharge & DQM
6. Precharge
7. Auto Precharge
1) BL=4 & tRDL = 2CLK
CMD
DQ
CLK
DQM
WR PRE
D
0
D
1
D
2
Masked by DQM
1) Normal Write
CMD
DQ
CLK
BL=4 & tRDL=2CLK
D
0
D
1
D
2
D
3
WR PRE
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD PRE
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
Auto Precharge Starts@tRDL=2CLK
3)
D
0
D
1
D
2
D
3
ACT
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
t
RDL