Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
58
MCP MEMORY
EXTENDED MODE REGISTER SET (EMRS)
1. For Internal TCSR, PASR and DS support
The extended mode register stores the data for selecting driver
strength and partial self refresh. EMRS cycle is not mandatory
and the EMRS command needs to be issued only when DS or
PASR is used. The default state without EMRS command issued
is half driver strength(for VDD 1.8V) / full driver strength(for VDD
2.5V, 3.0V) and all 4banks(full array) refreshed. The extended
mode register is written by asserting low on CS, RAS, CAS, WE
and high on BA1, low on BA0(The Mobile SDR SDRAM should
be in all bank precharge with CKE already high prior to writing
into the extended mode register). The state of address pins A0 ~
An in the same cycle as CS, RAS, CAS and WE going low is writ-
ten in the extended mode register. Two clock cycles are required
to complete the write operation in the extended mode register.
The mode register contents can be changed using the same
command and clock cycle requirements during operation as long
as all banks are in the idle state. A0 - A2 are used for partial self
refresh, A5 - A6 are used for Driver strength, "Low" on BA0 and
"High" on BA1 are used for EMRS. All the other address pins
except A0~A2, A5~A6, BA1, BA0 must be set to low for proper
EMRS operation. Refer to the table for specific codes.
2. For Internal TCSR, PASR support
The extended mode register stores the data for selecting partial
self refresh. EMRS cycle is not mandatory and the EMRS
command needs to be issued only when PASR is used. The
default state without EMRS command issued is all 4banks(full
array) refreshed. The extended mode register is written by
asserting low on CS, RAS, CAS, WE and high on BA1, low on
BA0(The Mobile SDR SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended mode
register). The state of address pins A0 ~ An in the same cycle as
CS, RAS, CAS and WE going low is written in the extended
mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register
contents can be changed using the same command and clock
cycle requirements during operation as long as all banks are in
the idle state. A0 - A2 are used for partial self refresh, "Low" on
BA0 and "High" on BA1 are used for EMRS. All the other
address pins except A0~A2, BA1, BA0 must be set to low for
proper EMRS operation. Refer to the table for specific codes.
BANK ACTIVATE.
The bank activate command is used to select a random row in an
idle bank. By asserting low on RAS and CS with desired row and
bank address, a row access is initiated. The read or write opera-
tion can occur after a time delay of t
RCD
(min) from the time of
bank activation. t
RCD
is an internal timing parameter of Mobile
SDR SDRAM, therefore it is dependent on operating clock fre-
quency. The minimum number of clock cycles required between
bank activate and read or write command should be calculated
by dividing t
RCD
(min) with cycle time of the clock and then round-
ing off the result to the next higher integer.
The Mobile SDR SDRAM has four internal banks in the same
chip and shares part of the internal circuitry to reduce chip area,
therefore it restricts the activation of four banks simultaneously.
Also the noise generated during sensing of each bank of Mobile
SDR SDRAM is high, requiring some time for power supplies to
recover before another bank can be sensed reliably. t
RRD
(min)
specifies the minimum time required between activating different
bank. The number of clock cycles required between different
bank activation must be calculated similar to t
RCD
specification.
The minimum time required for the bank to be active to initiate
sensing and restoring the complete row of dynamic cells is deter-
mined by t
RAS
(min). Every Mobile SDR SDRAM bank activate
command must satisfy t
RAS
(min) specification before a precharge
command to that active bank can be asserted. The maximum
time any bank can be in the active state is determined by
t
RAS
(max). The number of cycles for both t
RAS
(min) and
t
RAS
(max) can be calculated similar to t
RCD
specification.
Any system or application incorporating random access memory
products should be properly designed, tested and qulifided to
ensure proper use or access of such memory products. Dispro-
portionate, excessive and/or repeated access to a particular
address or addresses may result in reduction of product life.
A. DEVICE OPERATIONS (continued)