Samsung SC32442B54, Руководство пользователя

Страница: 563 / 647

K5D2G13ACM-D075
Revision 1.0
December 2006
8
MCP MEMORY
2K Bytes 64 Bytes
Figure 1. Functional Block Diagram
Figure 2. Array Organization
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle A
8
A
9
A
10
A
11
*L *L *L *L
3rd Cycle A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
4th Cycle A
20
A
21
A
22
A
23
A
24
A
25
A
26
A
27
5th Cycle A
28
*L *L *L *L *L *L *L
V
CC
X-Buffers
Command
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
V
SS
A
12
- A
28
A
0
- A
11
Command
CE
RE
WE
CLE
WP
I/0 0
I/0 7
V
CC
V
SS
128K Pages
(=2,048 Blocks)
2K Bytes
8 bit
64 Bytes
1 Block = 64 Pages
(128K + 4k) Byte
I/O 0 ~ I/O 7
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2,048 Blocks
= 2,112 Mbits
Row Address
Page Register
ALE
2,048M + 64M Bit
NAND Flash
ARRAY
(2,048 + 64)Byte x 131,072
Y-Gating
Row Address
Column Address
Column Address
Row Address
Data Register & S/A