Samsung SC32442B54, Руководство пользователя

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CLOCK & POWER MANAGEMENT SC32442B RISC MICROPROCESSOR
7
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16
Deep-STOP Mode
In Deep-STOP mode, Arm920T block is power off and all clocks of internal and pll are stopped for minimum
power consumption. Therefore, the PLL and oscillator circuit are also stopped. Just after exiting the Deep-STOP
mode, only NORMAL mode is available. In Figure 7-13-2, the user must return from Deep-STOP mode to
NORMAL mode. To exit from Deep-STOP mode, EINT, TICK or RTC alarm has to be activated and CLKCON
register is set properly. The sequence of Deep-Stop register is rCAMDIVN[16] = 1 and then rCLKCON[0]=1.
DRAM has to be in self-refresh mode during Deep-STOP mode to retain valid memory data.
LCD must be stopped before Deep-STOP mode, because DRAM can't be accessed when it’s in self-refresh
mode.
All interrupts should be masked, because DRAM can't be accessed when it’s in self-refresh mode.
(Even though all interrupts are masked, EINT can wake-up SC32442B with the setting of EXINT register.)
When wakeup the Deep-STOP, Arm jumped to reset handler, therefore, arm changed Fast mode. User must be
set to Async mode of ARM920T.
The SC32442B can exit from Deep-STOP mode by EINT(external interrupts), TICK or RTC alarm. During the
wake-up sequences, the crystal oscillator and PLL may begin to operate. The lock time is also needed to stabilize
FCLK. The lock time is inserted automatically and guaranteed by power management logic. During this lock time
the clock is not supplied. Just after wake-up sequences wake-up interrupt(RTC alarm, TICK or external interrupt)
is requested. The mode returns to normal mode re-written into the CLKCON register, immediately,
[rCLKCON[0]=1]
Figure7-12. Entering Deep-STOP Mode and Exiting Deep-STOP mode (Wake-up)