Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
49
MCP MEMORY
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Maximum burst refresh cycle : 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter Symbol 133Mhz@CL3 Unit Note
Row active to row active delay t
RRD
(min) 15 ns 1
RAS to CAS delay t
RCD
(min) 22.5 ns 1
Row precharge time t
RP
(min) 22.5 ns 1
Row active time
t
RAS
(min) 50 ns 1
t
RAS
(max) 100 us
Row cycle time t
RC
(min) 72.5 ns 1
Last data in to row precharge t
RDL
(min) 15 ns 2
Last data in to Active delay t
DAL
(min) tRDL + tRP -
Last data in to new col. address delay t
CDL
(min) 1 CLK 2
Last data in to burst stop t
BDL
(min) 1 CLK 2
Auto refresh cycle time t
ARFC
(min) 80 ns 3
Exit self refresh to active command t
SRFX
(min) 120 ns
Col. address to col. address delay t
CCD
(min) 1 CLK 4
Number of valid output data CAS latency=3 2 ea 5