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K5D2G13ACM-D075
Revision 1.0
December 2006
3
MCP MEMORY
GENERAL DESCRIPTION
FEATURES
Multi-Chip Package MEMORY
2G Bit (256Mx8) NAND Flash Memory / 512M Bit (4Mx32x4Banks) Mobile SDRAM
The K5D2G13ACM is a Multi Chip Package Memory which combines 2Gbit NAND Flash Memory and 512Mbit synchronous high data rate
Dynamic RAM. 2Gbit NAND Flash memory is organized as 256M x8 bits and 512Mbit Mobile SDRAM is organized as 4M x32 bits x4 banks.
Offered in 256Mx8bit, the NAND Flash is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective
solution for the solid state application market. A program operation can be performed in typical 200
µ
s on the (2K+64)Byte page and an erase
operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 45ns cycle time per Byte.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive
systems can take advantage of the device
′
s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with
real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage
and other portable applications requiring non-volatility.
The Mobile SDRAM is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 32 bits, fabricated
with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
The K5D2G13ACM is suitable for use in data memory of mobile communication system to reduce not only mount area but also power con-
sumption. This device is available in 119-ball FBGA Type.
<Mobile SDRAM>
• VDD/VDDQ = 1.8V/1.8V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
- CAS latency (1, 2 & 3).
- Burst length (1, 2, 4, 8 & Full page).
- Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
- PASR (Partial Array Self Refresh).
- Internal TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
Address configuration
Organization Bank Row Column
16M x32 BA0,BA1 A0 - A12 A0 - A8
<Common>
•
Operating Temperature : -25
°
C ~ 85
°
C
•
Package : 119-ball FBGA Type - 14x14x1.05mmt, 0.8mm pitch
<NAND Flash>
•
Voltage Supply : 1.7V ~ 1.95V
•
Organization
- Memory Cell Array : (256M + 8M) x 8bit
- Data Register : (2K + 64) x 8bit
•
Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
•
Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 25
µ
s(Max.)
- Serial Access : 45ns(Min.)
•
Fast Write Cycle Time
- Page Program time : 200
µ
s(Typ.)
- Block Erase Time : 1.5ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
-Endurance : 100K Program/Erase Cycles
(
with 1bit/512Byte ECC)
- Data Retention : 10 Years
•
Command Driven Operation
•
Intelligent Copy-Back with internal 1bit/528Byte EDC
•
Unique ID for Copyright Protection