Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
57
MCP MEMORY
CLOCK (CLK)
The clock input is used as the reference for all Mobile SDR
SDRAM operations. All operations are synchronized to the posi-
tive going edge of the clock. The clock transitions must be mono-
tonic between V
IL
and V
IH
. During operation with CKE high all
inputs are assumed to be in a valid state (low or high) for the
duration of set-up and hold time around positive edge of the
clock in order to function well and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto Mobile SDR
SDRAM. If CKE goes low synchronously with clock (set-up and
hold time are the same as other inputs), the internal clock is sus-
pended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes low.
When all banks are in the idle state and CKE goes low synchro-
nously with clock, the Mobile SDR SDRAM enters the power
down mode from the next clock cycle. The Mobile SDR SDRAM
remains in the power down mode ignoring the other inputs as
long as CKE remains low. The power down exit is synchronous
as the internal clock is suspended. When CKE goes high at least
"1CLK + tSS" before the high going edge of the clock, then the
Mobile SDR SDRAM becomes active from the same clock edge
accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the Mobile SDR SDRAM per-
forms no operation (NOP). NOP does not initiate any new opera-
tion, but is needed to complete operations which require more
than single clock cycle like bank activate, burst read, auto
refresh, etc. The device deselect is also a NOP and is entered by
asserting CS high. CS high disables the command decoder so
that RAS, CAS, WE and all the address inputs are ignored.
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the Mobile SDR SDRAM. Due to asynchro-
nous nature of the internal write, the DQM operation is critical to
avoid unwanted or incomplete writes when the complete burst
write is not required. Please refer to DQM timing diagram also.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of Mobile SDR SDRAM. It programs the CAS
latency, burst type, burst length, test mode and various vendor
specific options to make Mobile SDR SDRAM useful for variety
of different applications. The default value of the mode register is
not defined, therefore the mode register must be written after
power up to operate the Mobile SDR SDRAM. The mode regis-
ter is written by asserting low on CS, RAS, CAS and WE (The
Mobile SDR SDRAM should be in active mode with CKE already
high prior to writing the mode register). The state of address pins
A0 ~ An and BA0 ~ BA1 in the same cycle as CS, RAS, CAS and
WE going low is the data written in the mode register. Two clock
cycles is required to complete the write in the mode register. The
mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as
all banks are in the idle state. The mode register is divided into
various fields depending on the fields of functions. The burst
length field uses A0 ~ A2, burst type uses A3, CAS latency (read
latency from column address) use A4 ~ A6, vendor specific
options or test mode use A7 ~ A8, A10/AP ~ An and BA0 ~ BA1.
The write burst length is programmed using A9. A7 ~ A8, A10/AP
~ An and BA0 ~ BA1 must be set to low for normal Mobile SDR
SDRAM operation. Refer to the table for specific codes for vari-
ous burst length, burst type and CAS latencies.
A. DEVICE OPERATIONS (continued)