SC32442B RISC MICROPROCESSOR
LCD CONTROLLER
15-7
DITHERING AND FRAME RATE CONTROL
In case of STN LCD display (except monochrome), video data must be processed by a dithering algorithm. The
DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate
Control (FRC) for displaying gray and color level on the STN panel. The main principle of gray and color level
display on the STN panel based on FRC is described. For example, to display the third gray (3/16) level from a
total of 16 levels, the 3 times pixel should be on and 13 times pixel off. In other words, 3 frames should be
selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining
13 frames should have a pixel-off on a specific pixel. These 16 frames should be displayed periodically. This is
basic principle on how to display the gray level on the screen, so-called gray level display by FRC. The actual
example is shown in Table 15-2. To represent the 14
th
gray level in the table, we should have a 6/7 duty cycle,
which mean that there are 6 times pixel-on and one time pixel-off. The other cases for all gray levels are also
shown in Table 15-2.
In the STN LCD display, we should be reminded of one item, i.e., Flicker Noise due to the simultaneous pixel-on
and -off on adjacent frames. For example, if all pixels on first frame are turned on and all pixels on next frame are
turned off, the Flicker Noise will be maximized. To reduce the Flicker Noise on the screen, the average probability
of pixel-on and -off between frames should be the same. In order to realize this, the Time-based Dithering
Algorithm, which varies the pattern of adjacent pixels on every frame, should be used. This is explained in detail.
For the 16 gray level, FRC should have the following relationship between gray level and FRC. The 15
th
gray level
should always have pixel-on, and the 14
th
gray level should have 6 times pixel-on and one times pixel-off, and the
13
th
gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0
th
gray level should always
have pixel-off as shown in Table 15-2.
Table 15-2. Dither Duty Cycle Examples
Pre-dithered Data
(gray level number)
Duty Cycle
Pre-dithered Data
(gray level number)
Duty Cycle
15 1 7 1/2
14 6/7 6 3/7
13 4/5 5 2/5
12 3/4 4 1/3
11 5/7 3 1/4
10 2/3 2 1/5
9 3/5 1 1/7
8 4/7 0 0
Содержание SC32442B54
Страница 1: ...SC32442B54 USER S MANUAL Revision 1 0 ...
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Страница 59: ...PROGRAMMER S MODEL SC32442B RISC MICROPROCESSOR 2 16 NOTES ...
Страница 123: ...ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR 3 64 NOTES ...
Страница 167: ...THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR 4 44 NOTES ...
Страница 187: ...MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR 5 20 NOTES ...
Страница 250: ...DMA SC32442B RISC MICROPROCESSOR 8 14 NOTES ...
Страница 308: ...PWM TIMER SC32442B RISC MICROPROCESSOR 10 20 NOTES ...
Страница 330: ...UART SC32442B RISC MICROPROCESSOR 11 22 NOTES ...
Страница 417: ...SC32442B RISC MICROPROCESSOR LCD CONTROLLER 15 45 NOTES ...
Страница 427: ...ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR 16 10 NOTES ...
Страница 511: ...BUS PRIORITIES SC32442B RISC MICROPROCESSOR 24 2 NOTES ...
Страница 562: ...K5D2G13ACM D075 Revision 1 0 December 2006 7 MCP MEMORY 2Gb 256Mb x8 NAND Flash Memory A Die ...
Страница 599: ...K5D2G13ACM D075 Revision 1 0 December 2006 44 MCP MEMORY 512Mb 16Mb x32 Mobile SDRAM C Die ...