Samsung SC32442B54, Руководство пользователя

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ELECTRICAL DATA SC32442B RISC MICROPROCESSOR
25-38
(V
DDi,
V
DDiarm
= 1.7V
±
0.05 V, T
A
= -25 to 85
°
C, V
DDMOP
= 1.8V
±
0.1V, 125MHz, CL=25pF)
Parameter Symbol Min Typ Max Unit
SDRAM Address Delay
T
SAD
1.50 – 5.17 ns
SDRAM Chip Select Delay
T
SCSD
1.57 – 4.42 ns
SDRAM Row Active Delay
T
SRD
1.47 – 5.14 ns
SDRAM Column Active Delay
T
SCD
1.47 – 5.28 ns
SDRAM Byte Enable Delay
T
SBED
1.56 – 5.48 ns
SDRAM Write Enable Delay
T
SWD
1.59 – 5.28 ns
SDRAM Read Data Setup Time
T
SDS
2 – – ns
SDRAM Read Data Hold Time
T
SDH
1.5 – – ns
SDRAM Output Data Delay
T
SDD
1.39 – 5.39 ns
SDRAM Clock Enable Delay
T
cked
1.26 – 3.81 ns
note) This AC parameter is for 500M:125MHz case. At that time, VDDiarm/VDDi should have separated
voltage domain. V
DDiarm
= 1.7V
±
0.05 V, V
DDi
= 1.2V
±
0.05 V
(V
DDiarm
= 1.4V
±
0.05 V, V
DDi
= 1.2V
±
0.05 V T
A
= -25 to 85
°
C, V
DDMOP
= 1.8V
±
0.1V, 133MHz, CL=25pF)
Parameter Symbol Min Typ Max Unit
SDRAM Address Delay
T
SAD
1.02 – 5.17 ns
SDRAM Chip Select Delay
T
SCSD
1.11 – 4.42 ns
SDRAM Row Active Delay
T
SRD
1.08 – 5.14 ns
SDRAM Column Active Delay
T
SCD
1.05 – 5.28 ns
SDRAM Byte Enable Delay
T
SBED
1.07 – 5.48 ns
SDRAM Write Enable Delay
T
SWD
1.09 – 5.28 ns
SDRAM Read Data Setup Time
T
SDS
1.5 – – ns
SDRAM Read Data Hold Time
T
SDH
1.5 – – ns
SDRAM Output Data Delay
T
SDD
1 – 5.39 ns
SDRAM Clock Enable Delay
T
cked
0.88 – 3.81 ns