RL78/G1P
CHAPTER 11 SERIAL ARRAY UNIT
R01UH0895EJ0100 Rev.1.00
377
Nov 29, 2019
11.5.5 Slave reception
Slave reception is that the RL78/G1P receives data from another device in the state of a transfer clock being input from
another device.
3-Wire Serial I/O
CSI00
Target channel
Channel 0 of SAU0
Pins used
SCK00, SI00
Interrupt INTCSI00
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rate
Max. f
MCK
/6 [Hz]
Notes 1, 2
Data phase
Selectable by the DAPmn bit of the SCRmn register
DAPmn = 0: Data input starts from the start of the operation of the serial clock.
DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Non-reverse
CKPmn = 1: Reverse
Data direction
MSB or LSB first
Notes 1.
Because the external serial clock input to the SCK00 pin is sampled internally and used, the fastest transfer
rate is f
MCK
/6 [Hz].
2.
Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics in the electrical specifications (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS
).
Remarks 1.
f
MCK
: Operation clock frequency of target channel
f
SCK
: Serial clock frequency
2.
m: Unit number (m = 0), n: Channel number (n = 0), mn = 00