RL78/G1P
CHAPTER 26 INSTRUCTION SET
R01UH0895EJ0100 Rev.1.00
718
Nov 29, 2019
Table 26-5. Operation List (18/18)
Notes 1.
Number of CPU clocks (f
CLK
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2.
Number of CPU clocks (f
CLK
) when the program memory area is accessed.
3.
This indicates the number of clocks “when condition is not met/when condition is met”.
4.
n indicates the number of register banks (n = 0 to 3).
Remark
Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Instruction
Group
Mnemonic Operands Bytes Clocks
Operation
Flag
Note 1 Note 2
Z AC CY
Condition
al branch
BF saddr.bit,
$addr20
4
3/5
Note 3
PC
PC + 4 + jdisp8 if (saddr).bit = 0
sfr.bit, $addr20
4
3/5
Note 3
PC
PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr20
3
3/5
Note 3
PC
PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr20
4
3/5
Note 3
PC
PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr20
3
3/5
Note 3
6/7 PC
PC + 3 + jdisp8 if (HL).bit = 0
ES:[HL].bit,
$addr20
4 4/6
Note 3
7/8 PC
PC + 4 + jdisp8 if (ES, HL).bit = 0
BTCLR saddr.bit,
$addr20 4 3/5
Note 3
PC
PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
sfr.bit, $addr20
4
3/5
Note 3
PC
PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr20
3
3/5
Note 3
PC
PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr20
4
3/5
Note 3
PC
PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
× × ×
[HL].bit, $addr20
3
3/5
Note 3
PC
PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
ES:[HL].bit,
$addr20
4 4/6
Note 3
PC
PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
Conditional
skip
SKC
2 1
Next instruction skip if CY = 1
SKNC
2 1
Next instruction skip if CY = 0
SKZ
2 1
Next instruction skip if Z = 1
SKNZ
2 1
Next instruction skip if Z = 0
SKH
2 1
Next instruction skip if (Z
CY)=0
SKNH
2 1
Next instruction skip if (Z
CY)=1
CPU
control
SEL
Note 4
RBn
2
1
RBS[1:0]
n
NOP
1 1
No Operation
EI
3 4
IE
1 (Enable Interrupt)
DI
3 4
IE
0 (Disable Interrupt)
HALT
2 3
Set HALT Mode
STOP
2 3
Set STOP Mode