RL78/G1P
CHAPTER 11 SERIAL ARRAY UNIT
R01UH0895EJ0100 Rev.1.00
320
Nov 29, 2019
Figure 11-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address: F0118H, F0119H (SCR00), F011AH, F011BH (SCR01) After reset: 0087H R/W
Symbol 15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXE
mn
RXE
mn
DAP
mn
CKP
mn
0
EOC
mn
PTC
mn1
PTC
mn0
DIR
mn
0
SLCm
n1
Note 1
SLC
mn0
0 1
DLSm
n1
DLS
mn0
TXE
mn
RXE
mn
Setting of operation mode of channel n
0 0
Disable
communication.
0 1
Reception
only
1 0
Transmission
only
1 1
Transmission/reception
DAP
mn
CKP
mn
Selection of data and clock phase in CSI mode
Type
0 0
1
0 1
2
1 0
3
1 1
4
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode.
EOC
mn
Mask control of error interrupt signal (INTSREx (x = 0))
0
Disables generation of error interrupt INTSREx (INTSRx is generated).
1
Enables generation of error interrupt INTSREx (INTSRx is not generated if an error occurs).
Set EOCmn = 0 in the CSI mode and during UART transmission
Note 2
.
Notes 1.
The SCR00 register only.
2.
When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated.
Caution Be sure to clear bits 3, 6, and 11 to “0” (Also clear bit 5 of the SCR01 register to 0). Be sure to set bit
2 to “1”.
Remark
m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00)
D7
D6
D5
D4
D3
D2
D1
D0
SCKp
SOp
SIp input timing
D7
D6
D5
D4
D3
D2
D1
D0
SCKp
SOp
SIp input timing
D7
D6
D5
D4
D3
D2
D1
D0
SCKp
SOp
SIp input timing
D7
D6
D5
D4
D3
D2
D1
D0
SCKp
SOp
SIp input timing