RL78/G1P
CHAPTER 5 CLOCK GENERATOR
R01UH0895EJ0100 Rev.1.00
108
Nov 29, 2019
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
Address: F00F0H After reset: 00H R/W
Symbol
7 <6>
<5>
<4> 3 <2> 1 <0>
PER0
0
IICA1EN ADCEN IICA0EN
0
SAU0EN
0
TAU0EN
SAU0EN
Control of serial array unit 0 input clock supply
0
Stops input clock supply.
SFR used by the serial array unit 0 cannot be written.
The serial array unit 0 is in the reset status.
1
Enables input clock supply.
SFR used by the serial array unit 0 can be read and written.
TAU0EN
Control of timer array unit 0 input clock supply
0
Stops input clock supply.
SFR used by timer array unit 0 cannot be written.
Timer array unit 0 is in the reset status.
1
Enables input clock supply.
SFR used by timer array unit 0 can be read and written.
Caution
Be sure to clear bits 1, 3 and 7 to “0”.
Figure 5-8. Format of Peripheral Enable Register 1 (PER1)
Address: F007AH After reset: 00H R/W
Symbol
<7>
6 5 4 3 1 1 0
PER1
DACEN
0 0 0 0 0 0 0
DACEN
Control of D/A converter input clock supply
0
Stops input clock supply.
SFR used by the D/A converter cannot be written.
The D/A converter is in the reset status.
1
Enables input clock supply.
SFR used by the D/A converter can be read and written.
Caution
Be sure to clear bits 0 to 6 to “0”.