Renesas RL78/G1P, Руководство пользователя по оборудованию

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RL78/G1P CHAPTER 12 SERIAL INTERFACE IICA
R01UH0895EJ0100 Rev.1.00 485
Nov 29, 2019
12.4.2 Setting transfer clock by using IICWLn and IICWHn registers
(1) Setting transfer clock on master side
Transfer clock =
f
CLK
f
CLK
(t
R
+ t
F
)
At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows.
(The fractional parts of all setting values are rounded up.)

When the fast mode
IICWLn =
0.52
Transfer clock

f
CLK
IICWHn = (
0.48
Transfer clock

t
R

t
F
)

f
CLK

When the normal mode
IICWLn =
0.47
Transfer clock

f
CLK
IICWHn = (
0.53
Transfer clock

t
R

t
F
)

f
CLK

When the fast mode plus
IICWLn =
0.50
Transfer clock

f
CLK
IICWHn = (
0.50
Transfer clock

t
R

t
F
)

f
CLK
(2) Setting IICWLn and IICWHn registers on slave side
(The fractional parts of all setting values are truncated.)

When the fast mode
IICWLn = 1.3

s

f
CLK
IICWHn = (1.2

s

t
R

t
F
)

f
CLK

When the normal mode
IICWLn = 4.7

s

f
CLK
IICWHn = (5.3

s

t
R

t
F
)

f
CLK

When the fast mode plus
IICWLn = 0.50

s

f
CLK
IICWHn = (0.50

s

t
R

t
F
)

f
CLK
( Caution and Remarks are listed on the next page.)