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Appendix A
PI7C7100
3-Port PCI Bridge
A-7
04/18/00
ADVANCE INFORMATION
Addr
Addr
Addr
ByteEnables
ByteEnables
ByteEnables
6
6
6
Byte Enables
6
Addr
Data
Data
Data Data Data Data Data Data
6
Byte Enables
Addr
Data
Data
Data Data Data Data Data Data
Figure 10. Downstream Delayed Burst Memory Read Transaction ( P --> S )
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44 45
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44 45
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
P_CLK
P_AD [31:0]
P_CBE [3:0]
P_FRAME_L
P_IRDY_L
P_TRDY_L
P_STOP_L
P_DEVSEL_L
S_CLKOUT[0]
S_AD[31:0]
S_CBE[3:0]
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_STOP_L
S_DEVSEL_L
S_GNT_L
S_REQ_L
P_GNT_L
P_REQ_L
Addr
Data
Byte Enables
6
6
Addr
Byte Enables
Addr
Data
Byte Enables
6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
P_CLK
P_AD [31:0]
P_CBE [3:0]
P_FRAME_L
P_IRDY_L
P_TRDY_L
P_STOP_L
P_DEVSEL_L
S_CLKOUT[0]
S_AD[31:0]
S_CBE[3:0]
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_STOP_L
S_DEVSEL_L
S_GNT_L
S_REQ_L
P_GNT_L
P_REQ_L
Figure 11. Downstream Delayed Memory Read Transaction (P/33MHz-->S/33MHz)