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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev 1.1
4.8.4.3 Target Abort .......................................................................................................................................................... 27
4.9
Concurrent Mode Operation .................................................................................................................................. 27
5.
Address Decoding .................................................................................................................................................. 28
5.1
Address Ranges ..................................................................................................................................................... 28
5.2
I/O Address Decoding ........................................................................................................................................... 28
5.2.1
I/O Base and Limit Address Registers ................................................................................................................... 28
5.2.2
ISA Mode ............................................................................................................................................................... 29
5.3
Memory Address Decoding ................................................................................................................................... 29
5.3.1
Memory-Mapped I/O Base and Limit Address Registers ...................................................................................... 30
5.3.2
Prefetchable Memory Base and Limit Address Registers ...................................................................................... 30
5.4
VGA Support .......................................................................................................................................................... 31
5.4.1
VGA Mode ............................................................................................................................................................. 31
5.4.2
VGA Snoop Mode .................................................................................................................................................. 31
6.
Transaction Ordering ........................................................................................................................................... 32
6.1
Transactions Governed by Ordering Rules ........................................................................................................... 32
6.2
General Ordering Guidelines .................................................................................................................................. 32
6.3
Ordering Rules ....................................................................................................................................................... 33
6.4
Data Synchronization ............................................................................................................................................. 34
7.
Error Handling ...................................................................................................................................................... 35
7.1
Address Parity Errors ............................................................................................................................................. 35
7.2
Data Parity Errors ................................................................................................................................................... 35
7.2.1
Configuration Write Transactions to Configuration Space ................................................................................... 35
7.2.2
Read Transactions ................................................................................................................................................. 36
7.2.3
Delayed Write Transactions .................................................................................................................................. 36
7.2.4
Posted Write Transactions .................................................................................................................................... 38
7.3
Data Parity Error Reporting Summary .................................................................................................................... 39
7.4
System Error (SERR#) Reporting ........................................................................................................................... 45
8.
Exclusive Access ................................................................................................................................................... 46
8.1
Concurrent Locks ................................................................................................................................................... 46
8.2
Acquiring Exclusive Access across PI7C7100 ....................................................................................................... 46
8.3
Ending Exclusive Access ....................................................................................................................................... 47
9.
PCI Bus Arbitration .............................................................................................................................................. 48
9.1
Primary PCI Bus Arbitration ................................................................................................................................... 48
9.2
Secondary PCI Bus Arbitration ............................................................................................................................. 48
9.2.1
Secondary Bus Arbitration Using the Internal Arbiter .......................................................................................... 48
9.2.2
Secondary Bus Arbitration Using an External Arbiter ........................................................................................... 49
9.2.3
Bus Parking ............................................................................................................................................................ 49
10.
Clocks .................................................................................................................................................................... 50
10.1
Primary Clock Inputs .............................................................................................................................................. 50
10.2
Secondary Clock Outputs ...................................................................................................................................... 50
11.
Reset ...................................................................................................................................................................... 51
11.1
Primary Interface Reset .......................................................................................................................................... 51
11.2
Secondary Interface Reset ..................................................................................................................................... 51
11.3
Chip Reset .............................................................................................................................................................. 51
12.
Supported Commands ............................................................................................................................................ 52
12.1
Primary Interface .................................................................................................................................................... 52
12.2
Secondary Interface ............................................................................................................................................... 54
13.
Configuration Registers ....................................................................................................................................... 55
