Pericom PI7C7100, Руководство пользователя

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80
09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
l o b m y S r e t e m a r a P n o i t i d n o C . n i M . x a M s t i n U
T
W E K S
] 0 : 5 1 [ T U O K L C _ S g n o m a W E K S 0 0 . 1
s n
T
Y A L E D
] 0 : 5 1 [ T U O K L C _ S d n a K L C P n e e w t e b Y A L E D d a o l F p 0 2 7 0 1
T
E L C Y C
e m i t e l c y c ] 0 : 5 1 [ T U O K L C _ S , K L C P 0 3
T
H G I H
e m i t H G I H ] 0 : 5 1 [ T U O K L C _ S , K L C P 1 1
T
W O L
e m i t W O L ] 0 : 5 1 [ T U O K L C _ S , K L C P 1 1
16.4 Primary and Secondary Buses at 33 MHz Clock Timing
l o b m y S r e t e m a r a P . n i M . x a M s t i n U
T
u s
s l a n g i s d e s u b - K L C o t e m i t p u t e s t u p n I
3 , 2 , 1
7 –
s n
T
) p t p ( u s
t n i o p - o t - t n i o p - K L C o t e m i t p u t e s t u p n I
3 , 2 , 1
2 1 , 0 1 –
T
h
K L C m o r f e m i t d l o h l a n g i s t u p n I
2 , 1
0 –
T
l a v
s l a n g i s d e s u b - y a l e d d il a v l a n g i s o t K L C
3 , 2 , 1
2 1 1
T
) p t p ( l a v
t n i o p - o t - t n i o p - y a l e d d il a v l a n g i s o t K L C
3 , 2 , 1
2 2 1
T
n o
y a l e d e v i t c a o t t a o l F
2 , 1
2 –
T
f f o
y a l e d t a o l f o t e v i t c A
2 , 1
– 8 2
V
test
T
val
T
on
T
h
Valid
V
test
– 1.5V for 5V signals: 0.4 V
CC
for 3.3V signals
Valid
T
su
Input
Note:
Output
CLK
T
off
T
inval
Figure 16-1. PCI Signal Timing Measurement Conditions
16.5 Power Consumption
r e t e m a r a P l a c i p y T s t i n U
n o i t p m u s n o C r e w o P 0 0 6 W m
I , t n e r r u C y l p p u S
C C
2 8 1 A m
1. See Figure 16-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are synchronized to S_CLKOUT.
3. Point-to-point signals are p_req#, s1_req#<7:0>, s2_req#<7:0>, p_gnt#, s1_gnt#<7:0>, and s2_gnt#<7:0>. Bused signals
are p_ad, p_cbe#, p_par, p_perr#, p_serr#, p_frame#, p_irdy#, p_trdy#, p_lock#, p_devsel#, p_stop#, p_idsel, s1_ad,
s1_cbe#, s1_par, s1_perr#, s1_serr#, s1_frame#, s1_irdy#, s1_trdy#, s1_lock#, s1_devsel#, s1_stop#, s2_ad, s2_cbe#,
s3_par, s2_perr#, s2_serr#, s2_frame#, s2_irdy#, s2_trdy#, s2_lock#, s2_devsel#, and s2_stop#.
16.3 3.3V AC Specifications