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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
11. Reset
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
11.1 Primary Interface Reset
PI7C7100 has a reset input, P_RESET#. When P_RESET# is asserted, the following events occur:
• PI7C7100 immediately 3-states all primary and secondary PCI interface signals.
• PI7C7100 performs a chip reset.
• Registers that have default values are reset.
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLK.
11.2 Secondary Interface Reset
PI7C7100 is responsible for driving the secondary bus reset signals, S1_RESET# and S2_RESET#.
PI7C7100 asserts S1_RESET# or S2_RESET# when any of the following conditions is met:
• Signal P_RESET# is asserted.
Signal S1_RESET# or S2_RESET# remains asserted as long
as P_RESET# is asserted and does not de-assert until P_RESET# is de-asserted.
• The secondary reset bit in the bridge control register is set.
Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the
secondary reset bit.
• S1_RESET# or S2_RESET# pin is asserted.
When S1_RESET# or S2_RESET# is asserted, the following events occur:
PI7C7100 immediately 3-states all the secondary PCI interface signals associated with the Secondary
S1 or S2 port.
The S1_RESET# or S2_RESET# in asserting and de-asserting edges can be asynchronous to P_CLK.
• The chip reset bit in the diagnostic control register is set.
Signal S1_RESET# or S2_RESET# remains asserted until a configuration write operation clears the
secondary reset bit and the secondary clock serial mask has been shifted in.
When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control signals, including the secondary grant
outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven
low for the duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are
reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit, PI7C7100 remains accessible during
secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.
11.3 Chip Reset
The chip reset bit in the diagnostic control register can be used to reset PI7C7100 and the secondary buses. All registers,
and chip state machines are reset and all signals are 3-stated when the chip reset is set. In addition, S1_RESET# or
S2_RESET# is asserted, and the secondary reset bit is automatically set. Signal S1_RESET# or S2_RESET# remains
asserted until a configuration write operation clears the secondary reset bit.
As soon as chip reset completes, within 20 PCI clock cycles after completion of the configuration write operation that sets
the chip reset bit, the chip reset bit automatically clears and the chip is ready for configuration.
During chip reset, PI7C7100 is inaccessible.