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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write
transactions on the initiator bus, it is possible that the initiator’s re-attempts of the write transaction may not match the
original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout
condition may occur, possibly resulting in a system error (P_SERR# assertion).
For downstream transactions, when PI7C7100 is delivering data to the target on the secondary bus and S_PERR# is
asserted by the target, the following events occur:
•
PI7C7100 sets the secondary interface data parity detected bit in the secondary status register, if the
secondary parity error response bit is set in the bridge control register.
•
PI7C7100 captures the parity error condition to forward it back to the initiator on the primary bus.
Similarly, for upstream transactions, when PI7C7100 is delivering data to the target on the primary bus and P_PERR#
is asserted by the target, the following events occur:
•
PI7C7100 sets the primary interface data-parity-detected bit in the status register, if the primary parity-error-
response bit is set in the command register.
•
PI7C7100 captures the parity error condition to forward it back to the initiator on the secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same
address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data
queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed
transaction queues.
Two cases must be considered:
•
When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not
detected on the target bus
•
When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write
status to return, the following events occur:
•
PI7C7100 first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parity-
error-response bit is set in the command register.
•
PI7C7100 sets the primary interface parity-error-detected bit in the status register.
•
Because there was not an exact data and parity match, the write status is not returned and the transaction
remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has
write status to return, the following events occur:
•
PI7C7100 first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two cycles later, if the secondary
interface parity-error-response bit is set in the bridge control register (offset 3Ch).
•
PI7C7100 sets the secondary interface parity-error-detected bit in the secondary status register.
•
Because there was not an exact data and parity match, the write status is not returned and the transaction
remains in the queue.
For downstream transactions, where the parity error is being passed back from the target bus and the parity error
condition was not originally detected on the initiator bus, the following events occur:
•
PI7C7100 asserts P_PERR# two cycles after the data transfer, if the following are both true:
- The parity-error-response bit is set in the command register of the primary interface.
- The parity-error-response bit is set in the bridge control register of the secondary interface.
•
PI7C7100 completes the transaction normally.
