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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
When one of the last two events occurs, the PI7C7100 returns a target disconnect to the requesting initiator on this data
phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C7100 asserts its request on the target bus.
This can occur while PI7C7100 is still receiving data on the initiator bus. When the grant for the target bus is received and
the target bus is detected in the idle condition, PI7C7100 asserts FRAME# and drives the stored write address out on the
target bus. On the following cycle, PI7C7100 drives the first DWORD of write data and continues to transfer write data until
all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data
exists in the queue, PI7C7100 can drive one DWORD of write data each PCI clock cycle; that is, no master wait states
are inserted. If write data is flowing through PI7C7100 and the initiator stalls, PI7C7100 will signal the last data phase for
the current transaction at the target bus if the queue empties. PI7C7100 will restart the follow-on transactions if the queue
has new data.
PI7C7100 ends the transaction on the target bus when one of the following conditions is met:
• All posted write data has been delivered to the target.
• The target returns a target disconnect or target retry (PI7C7100 starts another transaction to deliver the rest of write data).
• The target returns a target abort (PI7C7100 discards remaining write data).
• The master latency timer expires, and PI7C7100 no longer has the target bus grant (PI7C7100 starts another transaction
to deliver remaining write data).
Section 4.8.3.2 provides detailed information about how PI7C7100 responds to target termination during posted write
transactions.
4.5.2 Memory Write and Invalidate Transactions
Posted write forwarding is used for Memory Write and Invalidate transactions.
PI7C7100 always converts Memory Write and Invalidate transactions to Memory Write transactions.
The PI7C7100 disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size
value in the cache line size register gives the number of DWORD in a cache line.
If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C7100 returns
a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills.
When the Memory Write and Invalidate transaction is disconnected before a cache line boundary is reached, typically
because the posted write buffer fills, the transaction is converted to Memory Write transaction.
4.5.3 Delayed Write Transactions
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions.
A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the
initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer.
When a write transaction is first detected on the initiator bus, and PI7C7100 forwards it as a delayed transaction, PI7C7100
claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7100
samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, PI7C7100 also samples
the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue.
The transaction is queued only if no other existing delayed transactions have the same address and command, and if the
delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction
queue and all ordering constraints with posted data are satisfied. The PI7C7100 initiates the transaction on the target bus.
PI7C7100 transfers the write data to the target. If PI7C7100 receives a target retry in response to the write transaction on
the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition
is encountered.
If PI7C7100 is unable to deliver write data after 2
24
(default) or 2
32
(maximum) attempts, PI7C7100 will report a system error.
PI7C7100 also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 7.4 for
information on the assertion of P_SERR#. When the initiator repeats the same write transaction (same command,
address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C7100
