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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev 1.1
13.2.49 Config Register 1 or 2: Successful I/O Write Count Register (read/write, bit 31-0; offset 84h) ............................. 69
13.2.50 Config Register 1 or 2: Successful Memory Read Count Register (read/write, bit 31-0; offset 88h) ..................... 69
13.2.51 Config Register 1 or 2: Successful Memory Write Count Register (read/write, bit 31-0; offset 8Ch) .................... 69
13.2.52 Config Register 1: Primary Successful I/O Read Count Register (read/write, bit 31-0; offset 90h) ....................... 69
13.2.53 Config Register 1: Primary Successful I/O Write Count Register (read/write, bit 31-0; offset 94h) ....................... 69
13.2.54 Config Register 1: Primary Successful Memory Read Count Register (read/write, bit 31-0; offset 98h) ............... 69
13.2.55 Config Register 1: Primary Successful Memory Write Count Register (read/write, bit 31-0; offset 9Ch) .............. 69
14.
Bridge Behavior .................................................................................................................................................... 70
14.1
Bridge Actions for Various Cycle Types ............................................................................................................... 70
14.2
Transaction Ordering ............................................................................................................................................. 70
14.3
Abnormal Termination (Initiated by Bridge Master) ............................................................................................. 71
14.3.1
Master Abort ......................................................................................................................................................... 71
14.3.2
Parity and Error Reporting ..................................................................................................................................... 71
14.3.3
Reporting Parity Errors ........................................................................................................................................... 71
14.3.4
Secondary IDSEL mapping .................................................................................................................................... 71
15.
IEEE 1149.1 Compatible JTAG Controller ........................................................................................................... 72
15.1
Boundary Scan Architecture ................................................................................................................................. 72
15.1.1
TAP Pins ................................................................................................................................................................ 72
15.1.2
Instruction Register ............................................................................................................................................... 72
15.2
Boundary Scan Instruction Set .............................................................................................................................. 73
15.3
TAP Test Data Registers ....................................................................................................................................... 74
15.4
Bypass Register ..................................................................................................................................................... 74
15.5
Boundary-Scan Register ......................................................................................................................................... 74
15.6
TAP Controller ....................................................................................................................................................... 74
16.
Electrical and Timing Specifications .................................................................................................................... 79
16.1
Maximum Ratings ................................................................................................................................................... 79
16.2
3.3V DC Specifications ........................................................................................................................................... 79
16.3
3.3V AC Specifications ........................................................................................................................................... 80
16.4
Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 80
16.5
Power Consumption ............................................................................................................................................... 80
17.
256-Pin PBGA Package ........................................................................................................................................... 81
17.1
Part Number Ordering Information ........................................................................................................................ 81
