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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Table 7–5. Assertion of P_PERR#
#
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x =don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 7–5 shows assertion of P_PERR#. This signal is set under the following conditions:
• PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus.
• The parity-error-response bit must be set in the command register of primary interface.
• PI7C7100 detects a data parity error on the primary bus or detects S_PERR# asserted during the completion
phase of a downstream delayed write transaction on the target (secondary) bus.