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Appendix A
PI7C7100
3-Port PCI Bridge
A-13
04/18/00
ADVANCE INFORMATION
Addr
Data
Data Data Data Data Data Data Data Data Data
Data
Data
Data Data Data Data Data Data Data Data
Byte Enables
Byte Enables
7
7
Addr
Figure 22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz-->P/33MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
P_CLK
P_AD [31:0]
P_CBE [3:0]
P_FRAME_L
P_IRDY_L
P_TRDY_L
P_STOP_L
P_DEVSEL_L
S_CLKOUT[0]
S_AD[31:0]
S_CBE[3:0]
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_STOP_L
S_DEVSEL_L
S_GNT_L
S_REQ_L
P_GNT_L
P_REQ_L
23
24
25
26
27
28
23
24
25
26
27
28
Addr
Data
Byte Enables
2
2
Addr
Byte Enables
Addr
Data
Byte Enables
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P_CLK
P_AD [31:0]
P_CBE [3:0]
P_FRAME_L
P_IRDY_L
P_TRDY_L
P_STOP_L
P_DEVSEL_L
S_CLKOUT[0]
S_AD[31:0]
S_CBE[3:0]
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_STOP_L
S_DEVSEL_L
S_GNT_L
S_REQ_L
P_GNT_L
P_REQ_L
23
24
25
26
Figure 23. Downstream Delayed I/O Read Transaction ( P --> S )