74
09/18/00 Rev 1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
15.3 TAP Test Data Registers
The PI7C7100 contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP
controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most significant bit.
TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on each rising
edge of TCK. While any register is selected, data is transferred from TDI to TDO without inversion. The following sections
describe each of the test data registers.
15.4 Bypass Register
The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass
instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can
be selected when no test operation is being performed on the PI7C7100.
15.5 Boundary-Scan Register
The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin.
Table 15-2 shows the bit order of the PI7C7100 boundary-scan register. All table cells that contain “Control” select the
direction of bidirectional pins or high-impedance output pins. When a “0” is loaded into the control cell, the associated
pin(s) are high-impedance or selected as input.
The boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and
connected between each of the PI7C7100’s pins and on-chip system logic. The VDD, GND, PLL, AGND, AVDD and JTAG
pins are NOT in the boundary-scan chain.
The boundary-scan register cells are dedicated logic and do not have any system function. Data may be loaded into the
boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample/
preload and extest instructions. Parallel loading takes place on the rising edge of TCK.
Data may be scanned into the boundary-scan register serially via the TDI serial input pin, clocked by the rising edge of
TCK. When the required data has been loaded into the master-cell stages, it can be driven into the system logic at input
pins or onto the output pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan register
by means of the TDO serial output pin at the falling edge of TCK.
15.6 TAP Controller
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that controls the sequence of test
logic operations. The TAP can be controlled via a bus master. The bus master can be either automatic test equipment
or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge
of TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes.
The TAP controller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAP controller can be
initialized by applying a high signal level on the TMS input for a minimum of five TCK periods.
For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public
instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available
from the IEEE).
