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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
13.2.7 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h)
Hardwired to 01h
13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h)
Hardwired to 060400h
13.2.9 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch)
This register is used when terminating memory write and invalidate transactions and when pre-fetching.
Only cache line sizes (in units of 4-byte) which are power of two are valid (only one bit can be set in this register;
only 00h, 01h, 02h, 04h, 08h, 10h are valid values). Reset to 00h
13.2.10 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)
This register sets the value for Master Latency Timer which starts counting when master asserts FRAME#. Reset to 00h
13.2.11 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch)
This register is implemented but not being used internally. Reset to 00h
13.2.12 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch)
Hardwired to 81h for function 0 (multiple function PCI-to-PCI bridge, for secondary bus S1)
13.2.13 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch)
Hardwired to 01h for function 1 (single function PCI-to-PCI bridge, for secondary bus S2)
13.2.14 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h)
Programmed with the number of the PCI bus to which the primary bridge interface is connected.
This value is set by software during configuration. Reset to 00h
13.2.15 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h)
This register is implemented but not being used internally. Reset to 00h
13.2.16 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h)
Programmed with the number of the PCI bridge secondary bus interface. This value is set by software during configu-
ration. Reset to 00h
13.2.17 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h)
Programmed with the number of the PCI bus with the highest number that is subordinate to the bridge.
This value is set by software during configuration. Reset to 00h
13.2.18 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h)
This register is programmed in units of PCI bus clocks.The latency timer checks for master accesses on the
secondary bus interfaces that remain unclaimed by any target. Reset to 00h
13.2.19 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch)
This register defines the bottom address of the I/O address range for the bridge. The upper four bits define the bottom
address range used by the chip to determine when to forward I/O transactions from one interface to the other. These
4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16]
are defined in the I/O base upper 16 bits address register. The address bits [11:0] are assumed to be 000h. The lower
four bits (3:0) of this register set to ‘0001’ (read-only) to indicate 32-bit I/O addressing. Reset to 00h
13.2.20 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch)
This register defines the top address of the I/O address range for the bridge. The upper four bits define the top
address range used by the chip to determine when to forward I/O transactions from one interface to the other. These
4 bits correspond to address bits [15:12] and are write-able. The upper 16 bits corresponding to address bits [31:16]
are defined in the I/O limit upper 16 bits address register. The address bits [11:0] are assumed to be FFFh. The lower
four bits (3:0) of this register set to ‘0001’ (read-only) to indicate 32-bit I/O addressing. Reset to 00h.
