14
09/18/00 Rev 1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
4.2 Single Address Phase
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on
P_CBE[3:0]. PI7C7100 supports the linear increment address mode only, which is indicated when the lowest two address bits
are equal to zero. If either of the lowest two address bits is nonzero, PI7C7100 automatically disconnects the transaction after
the first data transfer.
4.3 Device Select (DEVSEL#) Generation
PI7C7100 always performs positive address decoding (medium decode) when accepting transactions on either the primary or
secondary buses. PI7C7100 never does subtractive decode.
4.4 Data Phase
The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY# and
either TRDY# or STOP# are asserted. A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same
PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY#
are asserted, or when IRDY# and STOP# are asserted. See Section 4.8 for further discussion of transaction termination.
Depending on the command type, PI7C7100 can support multiple data phase PCI transactions. For a detailed description of
how PI7C7100 imposes disconnect boundaries, see Section 4.5.4 for write address boundaries and Section 4.6.3 read address
boundaries.
4.5 Write Transactions
Write transactions are treated as either posted write or delayed write transactions.
Table 4–2 shows the method of forwarding used for each type of write operation.
n
o
i
t
c
a
s
n
a
r
T
f
o
e
p
y
T
g
n
i
d
r
a
w
r
o
F
f
o
e
p
y
T
e
t
i
r
w
y
r
o
m
e
M
)
y
r
o
m
e
m
A
G
V
t
p
e
c
x
e
(
d
e
t
s
o
P
e
t
a
d
il
a
v
n
i
d
n
a
e
t
i
r
w
y
r
o
m
e
M
d
e
t
s
o
P
e
t
i
r
w
O
/
I
d
e
y
a
l
e
D
e
t
i
r
w
n
o
i
t
a
r
u
g
i
f
n
o
c
1
e
p
y
T
d
e
y
a
l
e
D
Table 4-2. Write Transaction Forwarding
4.5.1 Posted Write Transactions
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions.
When PI7C7100 determines that a memory write transaction is to be forwarded across the bridge, PI7C7100 asserts
DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough buffer space is available in the posted
memory write queue for the address and at least one DWORD of data. Under this condition, PI7C7100 accepts write data
without obtaining access to the target bus. The PI7C7100 can accept one DWORD of write data every PCI clock cycle.
That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently
delivered to the target.
The PI7C7100 continues to accept write data until one of the following events occurs:
• The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
• An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending
on the transaction type.
• The posted write data buffer fills up.
For timing diagrams, see Figures 15-22 and 27-30 in Appendix A
