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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Each bus master, including PI7C7100, can be configured to be in either the low priority group or the high priority group
by setting the corresponding priority bit in the arbiter-control register. The arbiter-control register is located at offset 40h.
Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is
set to 0, the master is assigned to the low priority group. If all the masters are assigned to one group, the algorithm defaults
to a straight rotating priority among all the masters. After reset, all external masters are assigned to the low priority group,
and PI7C7100 is assigned to the high priority group. PI7C7100 receives highest priority on the target bus every other
transaction, and priority rotates evenly among the other masters.
Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the start of each new transaction on
the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter asserts the grant signal
corresponding to the highest priority request that is asserted. If a grant for a particular request is asserted, and a higher
priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding
to the new higher priority request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is
assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that
initiated the last transaction now has the lowest priority in its group.
If PI7C7100 detects that an initiator has failed to assert S1_FRAME# or S2_FRAME# after 16 cycles of both grant assertion
and a secondary idle bus condition, the arbiter de-asserts the grant. That master does not receive any more grants until
it de-asserts its request for at least one PCI clock cycle.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle
in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than one PCI clock cycle later.
If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the
arbiter can de-assert one grant and assert another grant during the same PCI clock cycle.
9.2.2 Secondary Bus Arbitration Using an External Arbiter
The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is tied high. An external
arbiter must then be used.
When S_CFN# is tied high, PI7C7100 reconfigures four pins (two per port) to be external request and grant pins. The
S1_GNT#[0] and S2_GNT#[0] pins are reconfigured to be the external request pins because they are output. The
S1_REQ#[0] and S2_REQ#[0] pins are reconfigured to be the external grant pins because they are input. When an
external arbiter is used, PI7C7100 uses the S1_GNT#[0] or S2_GNT#[0] pin to request the secondary bus. When the
reconfigured S1_REQ#[0] or S2_REQ#[0] pin is asserted low after PI7C7100 has asserted S1_GNT#[0] or S2_GNT#[0].
PI7C7100 initiates a transaction on the secondary bus one cycle later. If grant is asserted and PI7C7100 has not asserted
the request, PI7C7100 parks AD, CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grant outputs, S1_GNT#[7:1] and S2_GNT#[7:1] are driven high. The unused secondary bus
request inputs, S1_REQ#[7:1] and S2_REQ#[7:1], should be pulled high.
9.2.3 Bus Parking
Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value while the bus is idle. In general,
the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus.
A device parks the bus when the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD
and CBE signals should be driven first, with the PAR signal driven one cycle later.
PI7C7100 parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the primary PCI bus is idle.
When P_GNT# is de-asserted, PI7C7100 3-states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle.
If PI7C7100 is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7100 can start the
transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI
bus. That is, PI7C7100 keeps the secondary bus grant asserted to a particular master until a new secondary bus request
comes along. After reset, PI7C7100 parks the secondary bus at itself until transactions start occurring on the secondary
bus. If the internal arbiter is disabled, PI7C7100 parks the secondary bus only when the reconfigured grant signal,
S_REQ#<0>, is asserted and the secondary bus is idle.
