44
09/18/00 Rev 1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Table 7–7 shows assertion of P_SERR#. This signal is set under the following conditions:
• PI7C7100 has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted
on a downstream posted write transaction.
• PI7C7100 did not detect the parity error as a target of the posted write transaction.
• The parity error response bit on the command register and the parity error response bit on the bridge control
register must both be set.
• The SERR# enable bit must be set in the command register.
Table 7–7. Assertion of P_SERR# for Data Parity Errors
#
R
R
E
S
_
P
n
o
i
t
c
a
s
n
a
r
T
e
p
y
T
n
o
i
t
c
e
r
i
D
s
a
w
r
o
r
r
e
e
r
e
h
w
s
u
B
d
e
t
c
e
t
e
d
y
r
a
d
n
o
c
e
S
/
y
r
a
m
i
r
P
s
t
i
b
e
s
n
o
p
s
e
r
r
o
r
r
e
y
t
i
r
a
p
)
d
e
t
r
e
s
s
a
-
e
d
(
1
d
a
e
R
m
a
e
r
t
s
n
w
o
D
y
r
a
m
i
r
P
x
/
x
1
1
d
a
e
R
m
a
e
r
t
s
n
w
o
D
y
r
a
d
n
o
c
e
S
x
/
x
1
d
a
e
R
m
a
e
r
t
s
p
U
y
r
a
m
i
r
P
x
/
x
1
d
a
e
R
m
a
e
r
t
s
p
U
y
r
a
d
n
o
c
e
S
x
/
x
1
e
t
i
r
w
d
e
t
s
o
P
m
a
e
r
t
s
n
w
o
D
y
r
a
m
i
r
P
x
/
x
0
2
)
d
e
t
r
e
s
s
a
(
e
t
i
r
w
d
e
t
s
o
P
m
a
e
r
t
s
n
w
o
D
y
r
a
d
n
o
c
e
S
1
/
1
0
3
e
t
i
r
w
d
e
t
s
o
P
m
a
e
r
t
s
p
U
y
r
a
m
i
r
P
1
/
1
1
e
t
i
r
w
d
e
t
s
o
P
m
a
e
r
t
s
p
U
y
r
a
d
n
o
c
e
S
x
/
x
1
e
t
i
r
w
d
e
y
a
l
e
D
m
a
e
r
t
s
n
w
o
D
y
r
a
m
i
r
P
x
/
x
1
e
t
i
r
w
d
e
y
a
l
e
D
m
a
e
r
t
s
n
w
o
D
y
r
a
d
n
o
c
e
S
x
/
x
1
e
t
i
r
w
d
e
y
a
l
e
D
m
a
e
r
t
s
p
U
y
r
a
m
i
r
P
x
/
x
1
e
t
i
r
w
d
e
y
a
l
e
D
m
a
e
r
t
s
p
U
y
r
a
d
n
o
c
e
S
x
/
x
1
x =don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.