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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
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Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section.
Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the
transactions pass each other.
The entries without superscripts reflect the PI7C7100’s implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and
the ordering rules are referred to by number in Table 6–1. These ordering rules apply to posted write transactions,
delayed write and read requests, and delayed write and read completion transactions crossing PI7C7100 in the same
direction. Note that delayed completion transactions cross PI7C7100 in the direction opposite that of the corresponding
delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator
bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write
transaction; if the second transaction were to complete before the first transaction, a device checking the flag could
subsequently consume stale data.
2. A delayed read request traveling in the same direction as a previously queued posted write transaction must push
the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read
request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if
the read transaction were to pass the write transaction, it would return stale data.
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction.
In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction
is on the same side of PI7C7100 as the target of the write transaction. The posted write transaction must complete to
the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of
the initiator of the posted write data and therefore should not complete until the write transaction is complete.
4. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the
delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request
were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume
stale data.
6.3 Ordering Rules
Table 6–1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow.
Table 6-1. Summary of Transaction Ordering
• Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing
in the other direction. PI7C7100 can accept posted write transactions on both interfaces at the same time, as well
as initiate posted write transactions on both interfaces at the same time.
• The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a
non-locked, non-posted transaction as a master. This is true for PI7C7100 and must also be true for other bus
agents. Otherwise, a deadlock can occur.
• PI7C7100 accepts posted write transactions, regardless of the state of completion of any delayed transactions
being forwarded across PI7C7100.
