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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Cycle type shown on each row is the subsequent cycle after the previous shown on the column.
?
n
m
u
l
o
C
s
s
a
p
w
o
R
n
a
C
W
M
P
1
n
m
u
l
o
C
R
R
D
2
n
m
u
l
o
C
R
W
D
3
n
m
u
l
o
C
C
R
D
4
n
m
u
l
o
C
C
W
D
5
n
m
u
l
o
C
)
1
w
o
R
(
W
M
P
o
N
s
e
Y
s
e
Y
s
e
Y
s
e
Y
)
2
w
o
R
(
R
R
D
o
N
o
N
o
N
s
e
Y
s
e
Y
)
3
w
o
R
(
R
W
D
o
N
o
N
o
N
s
e
Y
s
e
Y
)
4
w
o
R
(
C
R
D
o
N
s
e
Y
s
e
Y
o
N
o
N
)
5
w
o
R
(
C
W
D
s
e
Y
s
e
Y
s
e
Y
o
N
o
N
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must complete on the target bus in the
order in which they were received in the initiator bus.
In Row 2 Column 1, DRR cannot pass the previous PMW and that means the previous PMW heading to the same direction
must be completed before the DRR can be attempted on the target bus.
In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the head of the delayed transaction
queue.
14.3 Abnormal Termination (Initiated by Bridge Master)
14.3.1 Master Abort
Master abort indicates that when PI7C7100 acts as a master and receives no response (i.e., no target asserts
P_DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the bridge de-asserts FRAME# and then de-asserts
IRDY#.
14.3.2 Parity and Error Reporting
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, S1_PAR, and S2_PAR signals.
Parity should be even (i.e. an even number of ‘1’s) across AD, CBE, and PAR. Parity information on PAR is valid the cycle
after AD and CBE are valid. For reads, even parity must be generated using the initiators CBE signals combined with the
read data. Again, the PAR signal corresponds to read data from the previous data phase cycle.
14.3.3 Reporting Parity Errors
For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal by asserting
P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can only be asserted if bit 6 and
8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the
P_PERR# signal two cycles after the data phase and should remain asserted for one cycle when bit 8 in the Command
register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data
parity errors during read cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains
inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error
during a read cycle results in the bridge master initiating a Master Abort.
14.3.4 Secondary IDSEL mapping
When PI7C7100 detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type
1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at
P_AD[15:11] as a device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7100.
