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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev 1.1
List of Figures
1-1.
PI7C7100 on the System Board .................................................................................................................................... 2
1-2.
PI7C7100 in Redundant Applications .......................................................................................................................... 2
1-3.
PI7C7100 on Network Switching Hub .......................................................................................................................... 2
2-1.
PI7C7100 Block Diagram .............................................................................................................................................. 3
9-1.
Secondary Arbiter Example ....................................................................................................................................... 48
15-1. Test Access Port Block Diagram ............................................................................................................................... 72
16-1. PCI Signal Timing Measurement Conditions ............................................................................................................ 80
17-1. 256-Pin PBGA Package Drawing ................................................................................................................................ 81
List of Tables
4-1.
PCI Transaction ......................................................................................................................................................... 13
4-2.
Write Transaction Forwarding .................................................................................................................................. 14
4-3.
Write Transaction Disconnect Address Boundaries ................................................................................................ 16
4-4.
Read Pre-fetch Address Boundaries ......................................................................................................................... 17
4-5.
Read Transaction Pre-fetching .................................................................................................................................. 18
4-6.
Device Number to IDSEL S1_AD or S2_AD Pin Mapping ....................................................................................... 21
4-7.
Delayed Write Target Termination Response ........................................................................................................... 24
4-8.
Responses to Posted Write Target Termination ....................................................................................................... 25
4-9.
Responses to Delayed Read Target Termination ...................................................................................................... 25
6-1.
Summary of Tranaction Ordering .............................................................................................................................. 33
7-1.
Setting the Primary Interface Detected Parity Error Bit ............................................................................................. 39
7-2.
Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 40
7-3.
Setting the Primary Interface Data Parity Detected Bit .............................................................................................. 40
7-4.
Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 41
7-5.
Assertion of P_PERR# ............................................................................................................................................... 42
7-6.
Assertion of S_PERR# ............................................................................................................................................... 43
7-7.
Assertion of P_SERR# for Data Parity Errors ........................................................................................................... 44
15-1. TAP Pins .................................................................................................................................................................... 73
15-2. JTAG Boundary Register Order ................................................................................................................................ 75