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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read
transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read
transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the
initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator
terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes
first. When the buffer empties, PI7C7100 reflects the stalled condition to the initiator by de-asserting TRDY# until more
read data is available; otherwise, PI7C7100 does not insert any target wait states. When the initiator terminates the
transaction, PI7C7100 de-assertion of FRAME# on the initiator bus is forwarded to the target bus. Any remaining read data
is discarded.
PI7C7100 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed
transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable
through configuration register. If the initiator does not repeat the read transaction and before the discard timer expires (2
15
default), PI7C7100 discards the read transaction and read data from its queues. PI7C7100 also conditionally asserts
P_SERR# (see Section 7.4).
PI7C7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator
starts a read transaction that matches the address and read command of a read transaction that is already queued, the
current read command is not posted as it is already contained in the delayed transaction queue.
See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7100.
4.7 Configuration Transactions
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed
by configuration commands. All registers are accessible in configuration space only.
In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C7100 also
forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle
generation.
To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1.
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type
0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle
is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and
the lowest two address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register
to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of
a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type
1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI
bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction
is targeted. For timing diagrams, see Figures 1-8 in Appendix A.
4.7.1 Type 0 Access to PI7C7100
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration
space cannot be accessed from the secondary bus. The PI7C7100 responds to a Type 0 configuration transaction by
asserting P_DEVSEL# when the following conditions are met during the address phase:
• The bus command is a configuration read or configuration write transaction.
• Lowest two address bits P_AD[1:0] must be 00b.
• Signal P_IDSEL must be asserted.
Function code is either 0 for configuration space of S1, or 1 for configuration space of S2 as PI7C7100 is a multi-function
device.
PI7C7100 limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data
transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects,
all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits.
