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09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are
forwarded by PI7C7100 are driven as locked transactions on the target bus.
When PI7C7100 receives a target abort or a master abort in response to the delayed locked read transaction, this status
is passed back to the initiator, and no locks are established on either the target or the initiator bus. PI7C7100 resumes
forwarding unlocked transactions in both directions.
8.3 Ending Exclusive Access
After the lock has been acquired on both initiator and target buses, PI7C7100 must maintain the lock on the target bus
for any subsequent locked transactions until the initiator relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. On
subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. PI7C7100 does not know whether the
current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the LOCK# signal
at end of the transaction.
When the last locked transaction is a delayed transaction, PI7C7100 has already completed the transaction on the
secondary bus. In this example, as soon as PI7C7100 detects that the initiator has relinquished the LOCK# signal by
sampling it in the de-asserted state while FRAME# is de-asserted, PI7C7100 de-asserts the LOCK# signal on the target
bus as soon as possible. Because of this behavior, LOCK# may not be de-asserted until several cycles after the last locked
transaction has been completed on the target bus. As soon as PI7C7100 has de-asserted LOCK# to indicate the end of
a sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C7100 de-asserts LOCK# on the target bus at the end
of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus.
When PI7C7100 receives a target abort or a master abort in response to a locked delayed transaction, PI7C7100 returns
a target abort or a master abort when the initiator repeats the locked transaction. The initiator must then de-assert LOCK#
at the end of the transaction. PI7C7100 sets the appropriate status bits, flagging the abnormal target termination condition
(see Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed.
When PI7C7100 receives a target abort or a master abort in response to a locked posted write transaction, PI7C7100
cannot pass back that status to the initiator. PI7C7100 asserts SERR# on the initiator bus when a target abort or a master
abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal
SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see
Section 7.4).
