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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
9. PCI Bus Arbitration
PI7C7100 must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use
of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to
PI7C7100, typically on the motherboard. For the secondary PCI bus, PI7C7100 implements an internal arbiter. This arbiter
can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus
arbitration.
9.1 Primary PCI Bus Arbitration
PI7C7100 implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI bus arbitration.
PI7C7100 asserts P_REQ# when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus.
As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or
delayed transaction requests, PI7C7100 keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target
abort is received in response to a transaction initiated by PI7C7100 on the primary PCI bus, PI7C7100 de-asserts P_REQ#
for two PCI clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been completely queued.
When P_GNT# is asserted LOW by the primary bus arbiter after PI7C7100 has asserted P_REQ#, PI7C7100 initiates a
transaction on the primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7100 when P_REQ#
is not asserted, PI7C7100 parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus
is parked at PI7C7100 and PI7C7100 has a transaction to initiate on the primary bus, PI7C7100 starts the transaction if
P_GNT# was asserted during the previous cycle.
9.2 Secondary PCI Bus Arbitration
PI7C7100 implements an internal secondary PCI bus arbiter. This arbiter supports two sets of eight external masters in
addition to PI7C7100. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus
arbitration.
9.2.1 Secondary Bus Arbitration Using the Internal Arbiter
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW. PI7C7100 has two sets
of eight secondary bus request input pins, S1_REQ#[7:0], S2_REQ#[7:0], and two sets of eight secondary bus output
grant pins, S1_GNT#[7:0], S2_GNT#[7:0], to support external secondary bus masters. The secondary bus request and
grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN# is HIGH.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/
grants. Each set of masters can be assigned to a high priority group and a low priority group. The low priority group as
a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at
least every n+1 transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the
low priority group. Therefore, members of the high priority group can be serviced n transactions out of n+1, while one
member of the low priority group is serviced once every n+1 transactions. Figure 9–1 shows an example of an internal arbiter
where four masters, including PI7C7100, are in the high priority group, and five masters are in the low priority group. Using
this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion
B
m0
m1
m2
lpg
m3
m4
m5
m6
m7
Figure 9-1. Secondary Arbiter Example
(high priority members are given in italics, low priority members, in boldface type):
B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on.
