66
09/18/00 Rev 1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
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13.2.39 Configuration Register 1: Secondary Clock Control Register (bit 15-0; offset 68h)
13.2.40 Configuration Register 2: Secondary Clock Control Register (bit 15-0; offset 68h)
Note: R/W - Read/Write.