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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
5. Address Decoding
PI7C7100 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are
defined by base and limit address registers in the configuration space. This chapter describes these address ranges,
as well as ISA-
mode and VGA-addressing support.
5.1 Address Ranges
PI7C7100 uses the following address ranges that determine which I/O and memory transactions are forwarded from
the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus:
• Two 32-bit I/O address ranges
• Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
• Two 32-bit prefetchable memory address ranges
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI
buses. Transactions falling outside these ranges are forwarded upstream from the two secondary PCI buses to the
primary PCI bus.
No address translation is required in PI7C7100. The addresses that are not marked for downstream are always
forwarded upstream. However, if an address of a transaction initiated from S1 bus is located in the marked address
range for downstream in S2 bus and not in the marked address range for downstream in S1 bus, the transaction will
be forwarded to S2 bus instead of primary bus. By the same token, if an address of a transaction initiated from S2 bus
is located in the marked address range for downstream in S1 bus and not in the marked address range for downstream
in S2 bus, the transaction will be forwarded to S1 bus instead of primary bus.
5.2 I/O Address Decoding
PI7C7100 uses the following mechanisms that are defined in the configuration space to specify the I/O address space
for downstream and upstream forwarding:
• I/O base and limit address registers
• The ISA enable bit
• The VGA mode bit
• The VGA snoop bit
This section provides information on the I/O address registers and ISA mode.
Section 5.4 provides information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in
configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To
enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master-
enable bit is not set, PI7C7100 ignores all I/O and memory transactions initiated on the secondary bus. The master-
enable bit also allows upstream forwarding of memory transactions if it is set.
CAUTION
If any configuration state affecting I/O transaction forwarding is changed by a configuration write
operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus,
PI7C7100 response to the secondary bus I/O transactions is not predictable. Configure the I/O base and
limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master
enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
5.2.1 I/O Base and Limit Address Registers
PI7C7100 implements one set of I/O base and limit address registers in configuration space that define an I/O address
range per port downstream forwarding. PI7C7100 supports 32-bit I/O addressing, which allows I/O addresses
downstream of PI7C7100 to be mapped anywhere in a 4GB I/O address space.
