UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
189 of 362
NXP Semiconductors
UM10208
Chapter 15: LPC2800 GPDMA
When a DMA interrupt occurs, the Interrupt Service Routine (ISR) needs to:
1. Read the DMA_Stat Register to determine which channel(s) have encountered
potentially interrupting events. A good tactic at this point is to simply write the value
read back to the same register, to clear all of the conditions identified by 1s. The ISR
can then scan the value for 1s and deal with the event associated with each 1.
2. The ISR can determine which of the events identified by 1s in DMA_Stat actually
caused the current interrupt by reading the ISR Mask register, ones-complementing
its value, and ANDing the result with the value from DMA_Stat. 1s in that result
identify which condition(s) actually caused the current interrupt.
3. The main use of the “half-buffer” event is in conjunction with channels that have the
“circular buffer” bit set in their Configuration Registers. For such channels, both the
“half-complete” and “complete” interrupts should be enabled by 0s in the IQR Mask
register. The ISR can deal with such channels by examining the value from step 1 to
see whether the first half and/or second half of the buffer has been completed, and
either provide more output data in that half of the buffer, or copy the input data in that
half of the buffer to another area of memory.
4. At this point the ISR should read the Global Enable Register. If the value from step 1
includes an “end of list” and/or “AHB abort” condition, the ISR should proceed as
described in steps 5-9 to identify which channel(s) encountered the condition(s).
5. The ISR should maintain a private variable containing the value read from the Global
Enable Register at the time of the previous GPDMA interrupt. The ISR should and this
variable with the one’s complement of the current Global Enable value from step 4. 1s
in the result identify which channels have been disabled since the last interrupt.
6. The ISR can check each channel identified by a 1 in the result of step 5 for having
encountered an End of List interrupt by reading its Destination Address Register and
checking whether it contains the address of the DMA Software Interrupt Register
(0x8010 3C10). If so, that channel reached the end of its linked list.
7. The ISR can check each channel identified by a 1 in the result of step 5 (and not
meeting the check of step 6) for having encountered an AHB Abort condition by first
reading its Transfer Count register. The ISR can convert the Transfer Count to an
address displacement by reading the channel’s Configuration Register, isolating its
Size field, and shifting the Transfer Count value left by (2 minus the Size value) bits.
8. If the Configuration value indicates a memory Source, the ISR can try reading the
address formed by adding the channel’s Source Address Register and the address
displacement, using the data width identified by the Size value. If that read operation
results in a Data Abort exception, the current GPDMA channel saw the same Abort.
9. If the Configuration value indicates a memory Destination, the ISR can try writing the
address formed by adding the channel’s Destination Address Register and the
address displacement, using the data width identified by the Size value. If that write
operation results in a Data Abort exception, the current GPDMA channel saw the
same Abort.
10. Finally, to ensure that step 5 can be used for the next interrupt, the ISR should store
the value read from the Global Enable Register in step 4 in the private variable used
in step 5.