UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
128 of 362
1.
Features
•
Two general purpose timers, each with a 32-bit down counter.
•
The CGU provides a separate clock to each.
•
The CGU clock can be used directly, or prescale-divided by 16 or 256.
•
Free-running mode counts down from all ones.
•
Periodic mode counts down from the value in the Load register.
•
Interrupt request at zero count.
2.
Description
Timer 0 and Timer 1 are identical in capabilities. Each receives a separate clock from the
CGU’s APB1 clock domain, which is typically driven by the main PLL. If desired, software
could use the APB1 fractional divider to make the clocks for the two Timers operate at
different frequencies, but selectable prescaling by 1, 16, or 256 plus a 32-bit counter
should allow generation of any reasonable timing interval from the standard main PLL
clock. The timers always assert their interrupt requests when they count down to zero. If
interrupt is not desired the request(s) can be disabled in the interrupt controller.
3.
Register descriptions
3.1 Timer register map
UM10208
Chapter 10: Timer
Rev. 02 — 1 June 2007
User manual
Table 124. Timer registers
Names
Description
Access Reset
value
Addresses
T0LOAD
T1LOAD
Load Registers.
Writing to this address
immediately loads both the main 32-bit counter
and a 32-bit reload register, from which the main
counter can be reloaded when it has counted
down to 0. Reading this address reads the
reload register.
R/W
undefined
0x8002 0000
0x8002 0400
T0VALUE
T1VALUE
Value Registers.
Software can read the current
contents of the main 32-bit counter from this
read-only register at any time.
RO
undefined
0x8002 0004
0x8002 0404
T0CTRL
T1CTRL
Control Registers.
The four defined bits in this
register control the operation of the timer.
R/W
bit 7=0, all
others
undefined
0x8002 0008
0x8002 0408
T0CLR
T1CLR
Interrupt Clear Registers.
Writing any value to
this address clears the timer’s interrupt request.
WO
0x8002 000C
0x8002 040C
