UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
292 of 362
NXP Semiconductors
UM10208
Chapter 23: LPC2800 SD/MMC
•
To stop a data transfer when it reaches zero. This is the end of the data condition.
•
To start transferring a pending command (see
). This is used to send the
stop command for a stream data transfer.
The data block counter determines the end of a data block. If the counter is zero, the
end-of-data condition is TRUE (see
for more information).
4.3.9 Bus mode
In wide bus mode, all four data signals (MD3:0) are used to transfer data, and the CRC
code is calculated separately for each data signal. While transmitting data blocks to a
card, only MD0 is used for the CRC token and busy signalling. The start bit must be
transmitted on all four data signals at the same time (during the same clock period). If the
start bit is not detected on all data signals on the same clock edge while receiving data,
the DPSM sets the start bit error flag and moves to the IDLE state.
The data path also operates in half-duplex mode, where data is either sent to a card or
received from a card. While not being transferred, MD3:0 are in the hi-Z state.
Data on these signals is synchronous to the rising edge of the clock period.
If wide mode is not selected, the MD3:1 pins remain in hi-Z state (they can be assigned to
GPIO functions if only wide mode is used), and only MD0 is driven when data is
transmitted.
4.3.10 CRC token status
The CRC token status follows each write data block, and determines whether a card has
received the data block correctly. When the token has been received, the card asserts a
busy signal by driving MD0 low.
shows the CRC token status values.
Fig 37. Pending command start
data
counter
MCICLK
MCICMD
cmd state
MCIDAT0
CmdPend
3
2
1
0
7
6
5
4
3
2
1
Z
Z
Z
Z
Z
S
CMD
CMD
CMD
CMD
CMD
7
6
PEND
SEND
Table 327. CRC token status
Token
Description
010
Card has received an error-free data block.
101
Card has detected a CRC error.