UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
188 of 362
NXP Semiconductors
UM10208
Chapter 15: LPC2800 GPDMA
4.2.14 DMA Software Interrupt Register (DMA_SoftInt - 0x8010 3C10)
4.2.15 DMA Channel 3 External Enable Register (DMA3EXTEN - 0x8000 5040)
4.2.16 DMA Channel 5 External Enable Register (DMA5EXTEN - 0x8000 5044)
5.
Interrupt requests
GPDMA channels can request processor interrupts in 4 situations:
1. when a GPDMA channel completes transferring half of a buffer,
2. when a GPDMA channel completes transferring a buffer,
3. when two channels are used to follow a linked list, and the “list-handling” channel
comes to the end of the list, or
4. when any GPDMA channel encounters an AHB abort.
Whether the GPDMA block requests an interrupt in each of these situations is controlled
by the IRQ Mask Register. This register contains an individual Mask bit for each channel
for the conditions 1-2 above, but only a “global” Mask bit for all channels for conditions
3-4. Thus, software/firmware has a bit of a challenge to identify which channel
encountered an “end of list” or “AHB abort”.
Table 210. DMA Software Interrupt Register (DMA_SoftInt - 0x8010 3C10)
Bit
Symbol Description
Reset
Value
31:0
The GPDMA sets bit 30 in the DMA_Stat Register when this write-only
register is written. This feature is intended to be used by a linked-list
handling DMA channel to cause an interrupt when it has come to the end
of a linked list. See the following section for more about this register.
NA
Table 211. DMA Channel 3 External Enable Register (DMA3EXTEN - 0x8000 5040)
Bit
Symbol Description
Reset
Value
0
Writing a 1 to this bit subjects channel 3 to an external enable signal on
pin A20. After channel 3 has been set up for a transfer, a rising edge is
required on this pad before the channel begins operation. In addition to
this bit, pin A20 must be programmed as a GPIO input in the IO
configuration block (
).
0
31:1
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Table 212. DMA Channel 5 External Enable Register (DMA5EXTEN - 0x8000 5044)
Bit
Symbol Description
Reset
Value
0
Writing a 1 to this bit subjects channel 5 to an external enable signal on
pin A18. After channel 5 has been set up for a transfer, a rising edge is
required on this pad before the channel begins operation. In addition to
this bit, pin A18 must be programmed as a GPIO input in the IO
configuration block (
).
0
31:1
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.