UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
26 of 362
NXP Semiconductors
UM10208
Chapter 4: LPC2800 Cache
1. When data caching is enabled for a page, and another bus master such as the GPMA
uses this data as well.
2. When data caching is enabled for a page, and caching for this page is about to be
disabled. When the caching for a page is disabled, every word is read directly from
memory, bypassing the cache. If any data has been written to that page, the CPU may
read the wrong data.
3. When data caching in the CACHE_SETTINGS register is about to be disabled. This is
a more general version of case 2.
4. When the virtual address of a cached page is about to be changed. This applies for
both instruction and data caching. The cache controller is not aware of any changes
made to the address mapping. If the address mapping is changed, software must
ensure that any altered cache contents are flushed. Also, if code was executed from
the page that is about to be remapped, it must be flushed to prevent later execution of
the wrong instructions.
6.3 Avoiding cache flushing
It may be possible to avoid cache flushing in some cases. If the performance difference is
not critical, data caching can simply not be enabled. Performance reductions in the 20 to
30% range are possible if data caching is disabled, depending on the application.
Another way to avoid data caching in certain cases is to have 2 pages that point to the
same memory address range. One page would be set as cacheable, the other as not
cacheable. Data written to the non-cached page is written directly to memory, so other bus
masters can make use of this data without any need to flush the cache. Care must be
taken not to write data to one page, and read the same data from the other page. This can
be done by separating portions of the page that may be changing from portions that will
not be changing. Changeable portions would be both read and written in the non-cached
address range, while static data would be read from the cached address range.
6.4 CPU and cache clocking
The CPU clocking is somewhat different than the rest of the AHB system. Where the rest
of the AHB system is clocked by the CGU (the AHB-BASE_CLOCK, possibly modified by
a fractional divider), the CPU and cache system use the AHB clock as a reference to
generate internal clocks from the AHB_BASE_CLOCK. Inside the cache system is a
clock-gate that uses the reference clock to enable or disable the base clock going to the
CPU and cache system.
shows timing of some cases of different clock selection settings. These figures
show some internal signals to illustrate the timing. First, “CPU clock” is the clock as seen
by the CPU. Second, “CPU clock enable” is the signal that determines when the CPU
receives a clock when clock gating is enabled. The CPU clock enable signal goes low one
AHB clock prior to the time when the CPU clock is prevented.
Following is a description of each case shown:
1. CPU clock gating off, fractional divider not used.
In this case, there is no CPU clock-gating and a fractional divider for the AHB clock is
not selected. This results in a free-running clock for the AHB, cache and CPU, all
running at the same frequency. This is the reset condition of the system.
