UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
57 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
3.4 High speed PLL overview
The high speed PLL includes an optional initial divider stage, a multiplier stage, and an
optional final divider stage. Any of 5 input clocks can be selected as the input to the initial
divider. The output of the initial divider stage is the input to the multiplier, and the output of
the multiplier is the input to the final divider. The output of the final divider is the output of
the high speed PLL, and is one of the base clocks available to the selection stages.
The values by which the initial divider, multiplier, and final divider stages multiply or divide
their inputs are integers. They are related to (somewhat theoretical) numerical values
called NSEL, MSEL, and PSEL as shown in
.
The developer’s main task in using the HP PLL is to select a multiplier and dividers that
will allow the derivation of the desired output clock from one of the available input clocks.
This choice is constrained by the operating limitations of the multiplier stage. The
multiplier input clock must be between 4 kHz and 150 MHz, and the multiplier output clock
must be between 275 and 550 MHz.
If more than one combination of NSEL, MSEL, and PSEL can produce the desired clock
from one of the available input clocks, select among them as follows:
1. To maximize reliability of the Lock status bit and minimize startup time, choose
combinations in which the multiplier input clock is
between 100 kHz and 20 MHz.
2. If more than one combination remains after applying recommendation 1, choose
combinations that don’t involve initial division over those that do. This minimizes
phase noise and jitter.
3. If more than one combination remains after applying recommendation 2, there are two
possible approaches. First, a PLL oscillator frequency causes the PLL to consume
less power. For lower power operation, choose the settings that give the lowest
frequency of the multiplier output clock (in the range of 275 and 550 MHz). Second,
the PLL oscillator is most stable in the center of its frequency range, so the
combination for which the multiplier output frequency is closest to its center frequency
of 412 MHz can be used.
Many PLL modules, including the Main PLL described in the previous section, allow
software to program values like NSEL, MSEL, and PSEL directly into registers. However,
the high speed PLL requires that the multiplication and division factors be mapped to
specific control register values that are not obvious functions of the factors themselves.
The next section describes several ways of deriving these control register values.
3.5 Deriving Control Register Values from Multiplier and Divisor Factors
The initial division factor NSEL determines the value for control register HPNDEC. The
multiplication factor MSEL determines the values for the HPMDEC, HPSELR, HPSELI,
and HPSELP registers, and the final division factor PSEL determines the value for the
HPPDEC register. There are three ways of mapping from NSEL, MSEL, and PSEL to the
associated register values.
Table 39.
HS PLL Multiplication and Division Factors
Stage
Name of factor # bits xSEL Value
Multiplier/divisor
Initial divider NSEL
8
0-255
1-256
Multiplier
MSEL
15
0-32767 Even values 2-65536
Final divider PSEL
5
0-31
Even values 2-64
