UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
84 of 362
1.
Introduction
The LPC288x External Memory Controller (EMC) is a multi-port memory controller that
supports asynchronous static memory devices such as RAM, ROM and Flash, as well as
dynamic memories such as Single Data Rate SDRAM. It complies with ARM’s Advanced
Microcontroller Bus Architecture (AMBA).
2.
Features
•
Dynamic memory interface support including Single Data Rate SDRAM.
•
Asynchronous static memory device support including RAM, ROM, and Flash, with or
without asynchronous page mode.
•
Low transaction latency.
•
Read and write buffers to reduce latency and to improve performance.
•
8 bit and 16 bit static memory support.
•
16 bit SDRAM memory support.
•
Static memory features include:
–
Asynchronous page mode read.
–
Programmable wait states.
–
Bus turnaround delay.
–
Output enable, and write enable delays.
•
Extended wait.
•
One chip select for synchronous memory and three chip selects for static memory
devices.
•
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
•
Dynamic memory self-refresh mode controlled by software.
•
Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is
typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per device.
•
Separate reset domains allow for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
3.
Supported dynamic memory devices
This section provides examples of dynamic memory devices that are supported by the
EMC.
Note: This is not an exhaustive list of supported devices.
UM10208
Chapter 8: External Memory Controller (EMC)
Rev. 02 — 1 June 2007
User manual
