Motorola MPC860 PowerQUICC, Руководство пользователя

Страница: 546 / 1106

18-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
18.2.3.3 Timer Reference Registers (TRR1ÐTRR4)
Each timer reference register (TRR1ÐTRR4), shown in Figure 18-7, contains the timeoutÕs
reference value. The reference value is not reached until TCNx increments to equal the
timeout reference value.
18.2.3.4 Timer Capture Registers (TCR1ÐTCR4)
Each timer capture register (TCR1ÐTCR4), shown in Figure 18-8, is used to latch the value
of the counter according to TMRx[CE].
18.2.3.5 Timer Counter Registers (TCN1ÐTCN4)
Each timer counter register (TCN1ÐTCN4), shown in Figure 18-9, is an up-counter. A read
cycle to TCN1ÐTCN4 yields the current value of the timer, but does not affect the counting
operation. A write cycle to TCN1ÐTCN4 sets the register to the written value, thus causing
its corresponding prescaler, TMRx[PS], to be reset.
13Ð14 ICLK Input clock source for the timer.
00 Internally cascaded input.
For TMR1, the timer 1 input is the output of timer 2.
For TMR3, the timer 3 input is the output of timer 4.
For TMR2 and TMR4, this selection means no input clock is provided to the timer.
01 Internal general system clock.
10 Internal general system clock divided by 16.
11 Corresponding TIN
x signal (falling edge).
15 GE Gate enable.
0 TGATE
x is ignored.
1 TGATE x is used to control the timerÑTGATE1 for timer 1 and 2, TGATE2 for timer 3 and 4.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Timeout reference value
Reset 0xFFFF
R/W R/W
Addr 0x994 (TRR1), 0x996 (TRR2), 0x9A4 (TRR3), 0x9A6 (TRR4)
Figure 18-7. Timer Reference Registers (TRR1ÐTRR4)
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Latched counter value
Reset 0
R/W R/W
Addr 0x998 (TCR1), 0x99A (TCR2), 0x9A8 (TCR3), 0x9AA (TCR4)
Figure 18-8. Timer Capture Registers (TCR1ÐTCR4)
Table 18-2. TMR1ÐTMR4 Field Descriptions
Bits Name Description